FPGA RTL Design Engineer
Join us as we enable the third wave of computing in the data center using FPGAs! Megh was founded in 2017 by Intel veterans who pioneered the adoption of FPGAs in Data Center. We’re based in Hillsboro (just outside of Portland), Oregon, and have development offices in Bangalore, India. We offer a fast-paced, exciting work environment with competitive salaries and benefits. Our startup is rapidly maturing: we won the Technology Association of Oregon’s (TAO) 2019 Technology Company of the Year award in their Pre-Revenue category. We have taken the promise of heterogeneous computing with CPU and FPGA platforms from concept to production, delivering a solution that accelerates real-time analytics using FPGA accelerators in the public, private, and edge cloud.
Megh provides a platform for accelerating Real Time Analytics using Spark Streaming and other frameworks. We enable seamless acceleration of applications that process streams with Machine Learning and Deep Learning algorithms, extracting value from data as it is moving. Our solution supports both in-line processing and offloading of ML/DL libraries with FPGAs.
This position is located in Bangalore, India.
As a Design Engineer contributing to FPGA RTL team, you will be creating and verifying new Accelerated Functional Units (AFUs) that are part of a complete ingest, transform, and infer pipeline in the FPGAs. You will be developing and integrating components that are leading edge/pre-release technologies from multiple vendors and OEMs.
To apply, send your resume to email@example.com.
Primary responsibilities are to develop the FPGA RTL infrastructure to allow offload of compute-intensive algorithms on to FPGAs. This includes:
- Developing expertise in the big data/DL algorithms being offloaded
- Creating detailed design specifications that map the algorithms to an FPGA
- Implement and unit test design specifications in RTL
- Synthesize RTL to meet the timing and layout requirements for the FPGAs
- Working in a small team environment, with code reviews, to design and implement applications and SW infrastructure that is simple and clear, and with an eye to future maintenance.
Qualifications and experience
The following qualifications are required:
- BS/MS with 4-10 years relevant experience.
- Degree programs in CE, EE or similar technical field.
- Self-motivated, team player who is excited about working on leading edge technologies to solve customer’s problems and driving the success of the company.
- Development experience with RTL/HLS on FPGA/ASIC.
- Experience in development using VHDL, Verilog, and System Verilog languages.
- Knowledge of Linux user and/or kernel mode development.
- Strong technical and problem-solving skills.
- Strong written and verbal communications skills.
- Ability to define and execute tasks with limited direction.
The following qualifications are highly desirable:
- Experience with mapping various workloads to CPUs and accelerators, including implementing algorithms on FPGAs.
- Prior experience working with Heterogenous (FPGA, GPGPU) hardware systems.
- Experience in test or validation application development.
- Experience with new hardware/software integration and debugging.
- Experience with Jira and agile development methodologies.